SH7211 Datasheet, PDF (52/1228 Pages) Renesas Technology Corp – 32-Bit RISC Microcomputer SuperHTM RISC engine Family

Section 2 CPU
Addressing
Mode
Indexed GBR
indirect
Instruction
Format
Effective Address Calculation
@(R0, GBR) The effective address is the sum of GBR value
and R0.
GBR
+
GBR + R0
Equation
GBR + R0
R0
TBR duplicate
indirect with
displacement
@@
(disp:8,
TBR)
The effective address is the sum of TBR value
and an 8-bit displacement (disp). The value of
disp is zero-extended, and is multiplied by 4.
Contents of
address (TBR
+ disp × 4)
TBR
disp
+
(zero-extended)
×
4
TBR
+ disp × 4
(TBR
+ disp × 4)
PC indirect with @(disp:8,
displacement PC)
The effective address is the sum of PC value and
an 8-bit displacement (disp). The value of disp is
zero-extended, and is doubled for a word
operation, and quadrupled for a longword
operation. For a longword operation, the lowest
two bits of the PC value are masked.
PC
H'FFFFFFFC
disp
(zero-extended)
(for longword)
&
PC + disp × 2
+
or
PC & H'FFFFFFFC
+ disp × 4
×
Word:
PC + disp × 2
Longword:
PC &
H'FFFFFFFC +
disp × 4
2/4
Rev. 2.00 May. 08, 2008 Page 28 of 1200
REJ09B0344-0200