SH7211 Datasheet, PDF (749/1228 Pages) Renesas Technology Corp – 32-Bit RISC Microcomputer SuperHTM RISC engine Family

Section 16 I²C Bus Interface 3 (IIC3)
Section 16 I²C Bus Interface 3 (IIC3)
The I²C bus interface 3 conforms to and provides a subset of the Philips I²C (Inter-IC) bus
interface functions. However, the configuration of the registers that control the I²C bus differs
partly from the Philips register configuration.
16.1 Features
• Selection of I²C format or clocked synchronous serial format
• Continuous transmission/reception
Since the shift register, transmit data register, and receive data register are independent from
each other, the continuous transmission/reception can be performed.
I²C bus format:
• Start and stop conditions generated automatically in master mode
• Selection of acknowledge output levels when receiving
• Automatic loading of acknowledge bit when transmitting
• Bit synchronization/wait function
In master mode, the state of SCL is monitored per bit, and the timing is synchronized
automatically. If transmission/reception is not yet possible, set the SCL to low until
preparations are completed.
• Six interrupt sources
Transmit data empty (including slave-address match), transmit end, receive data full (including
slave-address match), arbitration lost, NACK detection, and stop condition detection
• The direct memory access controller (DMAC) can be activated by a transmit-data-empty
request or receive-data-full request to transfer data.
• Direct bus drive
Two pins, SCL and SDA pins, function as NMOS open-drain outputs when the bus drive
function is selected.
Clocked synchronous serial format:
• Four interrupt sources
Transmit-data-empty, transmit-end, receive-data-full, and overrun error
• The direct memory access controller (DMAC) can be activated by a transmit-data-empty
request or receive-data-full request to transfer data.
Rev. 2.00 May. 08, 2008 Page 725 of 1200
REJ09B0344-0200