SH7211 Datasheet, PDF (31/1228 Pages) Renesas Technology Corp – 32-Bit RISC Microcomputer SuperHTM RISC engine Family

1.2 Block Diagram
Section 1 Overview
SH-2A
CPU core
ROM
Cache
On-chip ROM
512 Kbytes
CPU instruction fetch bus (F bus)
CPU bus
(C bus)
CPU memory access bus (M bus) _{(I clock)}
On-chip RAM
32 Kbytes
Advanced
user debuger II
(AUD-II)
User break
controller
(UBC)
UBCTRG output
Internal bus (I bus) (B clock)
Bus state
controller
(BSC)
Port
External bus input/output
External bus width mode input
Peripheral
bus controller
Direct memory
access controller
(DMAC)
DREQ input
DACK output
TEND output
Peripheral bus (P clock)
Pin function
controller
(PFC)
I/O ports
Clock pulse
generator (CPG)
Interrupt
controller
(INTC)
Multi-function
timer pulse
unit 2
(MTU2)
Multi-function
timer pulse
unit 2
subset
(MTU2S)
Port output
enable 2
(POE2)
Compare
match timer
(CMT)
Port
Port
Port
General input/output EXTAL input,
XTAL output,
CK input/output,
Clock mode input
RES input,
MRES input,
NMI input,
IRQ input,
IRQOUT output
Port
Timer pulse
input/output
Port
Timer pulse
input/output
Port
POE input
High-performance
user debugging
interface
(H-UDI)
Power-down
mode
control
8-bit
D/A converter
(DAC)
12-bit
A/D converter
(ADC)
I²C bus
interface 3
(IIC3)
Serial
communication
interface
with FIFO
(SCIF)
Watchdog
timer
(WDT)
WAVE
interface
(WAVEIF)
Port
JTAG input/output
Port
Analog output
Port
Analog input,
ADTRG input
Port
I²C bus
input/output
Port
Port
Port
Serial input/output WDTOVF output WAVE input/output
Figure 1.1 Block Diagram
Rev. 2.00 May. 08, 2008 Page 7 of 1200
REJ09B0344-0200