SH7211 Datasheet, PDF (18/1228 Pages) Renesas Technology Corp – 32-Bit RISC Microcomputer SuperHTM RISC engine Family

14.5.3 System Reset by WDTOVF Signal....................................................................... 663
14.5.4 Manual Reset in Watchdog Timer Mode.............................................................. 664
Section 15 Serial Communication Interface with FIFO (SCIF)..........................665
15.1 Features.............................................................................................................................. 665
15.2 Input/Output Pins............................................................................................................... 667
15.3 Register Descriptions ......................................................................................................... 668
15.3.1 Receive Shift Register (SCRSR) .......................................................................... 670
15.3.2 Receive FIFO Data Register (SCFRDR) .............................................................. 670
15.3.3 Transmit Shift Register (SCTSR) ......................................................................... 671
15.3.4 Transmit FIFO Data Register (SCFTDR) ............................................................. 671
15.3.5 Serial Mode Register (SCSMR)............................................................................ 672
15.3.6 Serial Control Register (SCSCR).......................................................................... 675
15.3.7 Serial Status Register (SCFSR) ............................................................................ 679
15.3.8 Bit Rate Register (SCBRR) .................................................................................. 687
15.3.9 FIFO Control Register (SCFCR) .......................................................................... 692
15.3.10 FIFO Data Count Register (SCFDR) .................................................................... 694
15.3.11 Serial Port Register (SCSPTR) ............................................................................. 695
15.3.12 Line Status Register (SCLSR) .............................................................................. 696
15.3.13 Serial Extended Mode Register (SCSEMR) ......................................................... 698
15.4 Operation ........................................................................................................................... 699
15.4.1 Overview .............................................................................................................. 699
15.4.2 Operation in Asynchronous Mode ........................................................................ 701
15.4.3 Operation in Clocked Synchronous Mode ............................................................ 711
15.5 SCIF Interrupts .................................................................................................................. 720
15.6 Usage Notes ....................................................................................................................... 721
15.6.1 SCFTDR Writing and TDFE Flag ........................................................................ 721
15.6.2 SCFRDR Reading and RDF Flag ......................................................................... 721
15.6.3 Restriction on DMAC Usage ................................................................................ 722
15.6.4 Break Detection and Processing ........................................................................... 722
15.6.5 Sending a Break Signal......................................................................................... 722
15.6.6 Receive Data Sampling Timing and Receive Margin (Asynchronous Mode) ...... 723
15.6.7 FER and PER Flags in the Serial Status Register (SCFSR).................................. 724
Section 16 I²C Bus Interface 3 (IIC3).................................................................. 725
16.1 Features.............................................................................................................................. 725
16.2 Input/Output Pins............................................................................................................... 727
16.3 Register Descriptions ......................................................................................................... 728
16.3.1 I²C Bus Control Register 1 (ICCR1)..................................................................... 729
16.3.2 I²C Bus Control Register 2 (ICCR2)..................................................................... 732
Rev. 2.00 May. 08, 2008 Page xviii of xxiv
REJ09B0344-0200