SH7211 Datasheet, PDF (77/1228 Pages) Renesas Technology Corp – 32-Bit RISC Microcomputer SuperHTM RISC engine Family

Section 2 CPU
Instruction
Instruction Code Operation
Execu-
Compatibility
tion
SH2,
Cycles T Bit SH2E SH4 SH-2A
BXOR.B #imm3,@(disp12,Rn) 0011nnnn0iii1001 (imm of (disp + Rn)) ^ T → T 3
Ope-
Yes
0110dddddddddddd
ration
result
2.5 Processing States
The CPU has five processing states: reset, exception handling, bus-released, program execution,
and power-down. Figure 2.6 shows the transitions between the states.
Power-on reset from any state
Manual reset from any state
Power-on reset state
Manual reset state
Reset canceled
Reset state
Interrupt source or
DMA address error occurs
Exception
handling state
Bus request
cleared
Bus request
generated
Exception
handling
source
occurs
Exception
handling
ends
Bus-released state
Bus request
cleared
Bus request
generated
Program execution state
Bus request Bus request
generated
cleared
STBY bit cleared
for SLEEP
instruction
NMI interrupt or
IRQ interrupt occurs
STBY bit set
for SLEEP
instruction
Sleep mode
Software standby mode
Power-down state
Figure 2.6 Transitions between Processing States
Rev. 2.00 May. 08, 2008 Page 53 of 1200
REJ09B0344-0200