SH7211 Datasheet, PDF (276/1228 Pages) Renesas Technology Corp – 32-Bit RISC Microcomputer SuperHTM RISC engine Family

Section 8 Bus State Controller (BSC)
be specified as 1 to 4 cycles. This CAS latency can be achieved by connecting a latch circuit
between this LSI and the SDRAM.
A Tde cycle is an idle cycle required to transfer the read data into this LSI and occurs once for
every burst read or every single read.
CK
A25 to A0
A12/A11*¹
CSn
RASL, RASU
CASL, CASU
RD/WR
DQMxx
D15 to D0
BS
DACKn*²
Td1 Td2
Td3
Td4
Tr
Tc1
Tc2
Tc3
Tc4
Tde (Tap)
Notes: 1. Address pin to be connected to pin A10 of SDRAM.
2. The waveform for DACKn is when active low is specified.
Figure 8.14 Burst Read Basic Timing (CAS Latency 1, Auto-Precharge)
Rev. 2.00 May. 08, 2008 Page 252 of 1200
REJ09B0344-0200