SH7211 Datasheet, PDF (169/1228 Pages) Renesas Technology Corp – 32-Bit RISC Microcomputer SuperHTM RISC engine Family

Section 7 User Break Controller (UBC)
7.2 Input/Output Pin
Table 7.1 shows the pin configuration of the UBC.
Table 7.1 Pin Configuration
Pin Name
UBC trigger
Symbol
UBCTRG
I/O
Output
Function
Indicates that a setting condition is
satisfied on either channel 0, 1, 2, or 3 of
the UBC.
7.3 Register Descriptions
The UBC has the following registers.
Table 7.2 Register Configuration
Channel Register Name
0
Break address register_0
Break address mask register_0
Break bus cycle register_0
1
Break address register_1
Break address mask register_1
Break bus cycle register_1
2
Break address register_2
Break address mask register_2
Break bus cycle register_2
3
Break address register_3
Break address mask register_3
Break bus cycle register_3
Common Break control register
Abbrevia-
tion
BAR_0
BAMR_0
BBR_0
BAR_1
BAMR_1
BBR_1
BAR_2
BAMR_2
BBR_2
BAR_3
BAMR_3
BBR_3
BRCR
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
Initial Value
H'00000000
H'00000000
H'0000
H'00000000
H'00000000
H'0000
H'00000000
H'00000000
H'0000
H'00000000
H'00000000
H'0000
H'00000000
Address
Access
Size
H'FFFC0400 32
H'FFFC0404 32
H'FFFC04A0 16
H'FFFC0410 32
H'FFFC0414 32
H'FFFC04B0 16
H'FFFC0420 32
H'FFFC0424 32
H'FFFC04A4 16
H'FFFC0430 32
H'FFFC0434 32
H'FFFC04B4 16
H'FFFC04C0 32
Rev. 2.00 May. 08, 2008 Page 145 of 1200
REJ09B0344-0200