SH7211 Datasheet, PDF (362/1228 Pages) Renesas Technology Corp – 32-Bit RISC Microcomputer SuperHTM RISC engine Family

Section 9 Direct Memory Access Controller (DMAC)
CK
A25 to A0
CSn
Transfer source
address
Transfer destination
address
D31 to D0
RD
WEn
DACKn
(Active-low)
Data read cycle
(1st cycle)
Data write cycle
(2nd cycle)
Note: In transfer between external memories, with DACK output in the read cycle,
DACK output timing is the same as that of CSn.
Figure 9.6 Example of DMA Transfer Timing in Dual Mode
(Transfer Source: Normal Memory, Transfer Destination: Normal Memory)
Rev. 2.00 May. 08, 2008 Page 338 of 1200
REJ09B0344-0200