SH7211 Datasheet, PDF (735/1228 Pages) Renesas Technology Corp – 32-Bit RISC Microcomputer SuperHTM RISC engine Family

Section 15 Serial Communication Interface with FIFO (SCIF)
Serial
data
Start
1 _bit
0 D0
Data
Parity Stop Start
bit bit bit
D1
D7 0/1 1
0 D0
Data
Parity Stop
bit
bit
1
D1
D7
0/1 1
Idle state
(mark state)
RDF
FER
RXI interrupt
request
One frame
Data read and RDF flag
read as 1 then cleared to 0
by RXI interrupt handler
ERI interrupt request
generated by receive
error
Figure 15.8 Example of SCIF Receive Operation
(8-Bit Data, Parity, 1 Stop Bit)
15.4.3 Operation in Clocked Synchronous Mode
In clocked synchronous mode, the SCIF transmits and receives data in synchronization with clock
pulses. This mode is suitable for high-speed serial communication.
The SCIF transmitter and receiver are independent, so full-duplex communication is possible
while sharing the same clock. The transmitter and receiver are also 16-byte FIFO buffered, so
continuous transmitting or receiving is possible by reading or writing data while transmitting or
receiving is in progress.
Figure 15.9 shows the general format in clocked synchronous serial communication.
*
Serial clock
One unit of transfer data (character or frame)
*
LSB
Serial data Don't care Bit 0
Bit 1
Bit 2
Bit 3
Bit 4
Bit 5
Bit 6
MSB
Bit 7 Don't care
Note: * High except in continuous transfer
Figure 15.9 Data Format in Clocked Synchronous Communication
Rev. 2.00 May. 08, 2008 Page 711 of 1200
REJ09B0344-0200