SH7211 Datasheet, PDF (422/1228 Pages) Renesas Technology Corp – 32-Bit RISC Microcomputer SuperHTM RISC engine Family

Section 10 Multi-Function Timer Pulse Unit 2 (MTU2)
• TSR2_0
Bit: 7
6
5
4
3
2
1
0
-
-
-
-
-
- TGFF TGFE
Initial value: 1
1
0
0
0
0
0
0
R/W: R
R
R
R
R
R R/(W)*¹ R/(W)*¹
Note: 1. Writing 0 to this bit after reading it as 1 clears the flag and is the only allowed way.
Initial
Bit
Bit Name Value R/W Description
7, 6 —
All 1
R
Reserved
These bits are always read as 1. The write value
should always be 1.
5 to 2 —
All 0
R
Reserved
These bits are always read as 0. The write value
should always be 0.
1
TGFF
0
R/(W)*¹ Compare Match Flag F
Status flag that indicates the occurrence of compare
match between TCNT_0 and TGRF_0.
[Clearing condition]
• When 0 is written to TGFF after reading
TGFF = 1*²
[Setting condition]
0
TGFE
0
• When TCNT_0 = TGRF_0 and TGRF_0 is
functioning as compare register
R/(W)*¹ Compare Match Flag E
Status flag that indicates the occurrence of compare
match between TCNT_0 and TGRE_0.
[Clearing condition]
• When 0 is written to TGFE after reading
TGFE = 1*²
[Setting condition]
• When TCNT_0 = TGRE_0 and TGRE_0 is
functioning as compare register
Notes: 1. Writing 0 to this bit after reading it as 1 clears the flag and is the only allowed way.
2. When writing to the timer status register (TSR), write 0 to the bit to be cleared after
reading 1. Write 1 to other bits. But 1 is not actually written and the previous value is
held.
Rev. 2.00 May. 08, 2008 Page 398 of 1200
REJ09B0344-0200