SH7211 Datasheet, PDF (1130/1228 Pages) Renesas Technology Corp – 32-Bit RISC Microcomputer SuperHTM RISC engine Family

Section 27 Electrical Characteristics
CK
A25 to A0
CSn
RD/WR
RD
T1
Tw
t_AD1
t_CSD1 t_AS
tRWD1
t_RSD
D15 to D0
Twx
T2B
Twb
T2B
t_AD2
tAD2
t_AD1
t_CSD1
tRDS3
t_RDH3
t_RWD1
t_RSD
t_RDS3
t_RDH3
WEn
BS
DACKn
TENDn*
WAIT
t_BSD
t_BSD
t_DACD
t_WTH
t_WTH
t_WTS
t_WTS
tDACD
Note: * The waveform for DACKn and TENDn is when active low is specified.
Figure 27.19 Burst ROM Read Cycle
(One Software Wait Cycle, One Asynchronous External Burst Wait Cycle, Two-Cycle Burst)
Rev. 2.00 May. 08, 2008 Page 1106 of 1200
REJ09B0344-0200