SH7211 Datasheet, PDF (958/1228 Pages) Renesas Technology Corp – 32-Bit RISC Microcomputer SuperHTM RISC engine Family

Section 21 Flash Memory
(3.4) The return value in the erasing program, FPFR (general register R0) is checked.
(3.5) Determine whether erasure of the necessary blocks has finished.
If more than one block is to be erased, update the FEBS parameter and repeat steps (3.2) to
(3.5). Blocks that have already been erased can be erased again.
(3.6) After erasure finishes, clear FKEY and specify software protection.
If this LSI is restarted by a power-on reset immediately after user MAT erasing has finished,
secure a reset period (period of RES = 0) that is at least as long as the normal 100 μs.
(4) Erasing and Programming Procedure in User Program Mode
By changing the on-chip RAM address of the download destination in FTDAR, the erasing
program and programming program can be downloaded to separate on-chip RAM areas.
Figure 21.13 shows an example of repetitively executing RAM emulation, erasing, and
programming.
Start procedure program
1
Set FTDAR to H'00
(Specify H'FFF81000 as
download destination)
Download erasing program
Initialize erasing program
Set FTDAR to H'02
(Specify H'FFF82000 as
download destination)
Erase relevant block
(execute erasing program)
Set FMPDR to H'FFF86000 to
program relevant block
(execute programming program)
Confirm operation
Download programming
program
Initialize programming
program
1
End?
No
Yes
End procedure program
Figure 21.13 Sample Procedure of Repeating RAM Emulation, Erasing, and Programming
(Overview)
Rev. 2.00 May. 08, 2008 Page 934 of 1200
REJ09B0344-0200