SH7211 Datasheet, PDF (34/1228 Pages) Renesas Technology Corp – 32-Bit RISC Microcomputer SuperHTM RISC engine Family

Section 1 Overview
Classification
Operating mode
control
System control
Symbol
I/O Name
Function
MD1, MD0 I
Mode set
Sets the operating mode. Do not
change the signal levels on these
pins during operation.
MD_CLK2, I
MD_CLK0
Clock mode set
Sets the clock operating mode. Do
not change the signal levels on these
pins during operation.
FWE
ASEMD
I
Flash memory Pin for flash memory. Flash memory
write enable
can be protected against writing or
erasure through this pin.
I
Debugging mode Enables the E10A-USB emulator
functions.
Input a high level to operate the LSI
in normal mode (not in debugging
mode). To operate it in debugging
mode, apply a low level to this pin on
the user system board.
TESTMD I
Test mode
Always fix this input pin low.
RES
MRES
Do not input a high level to this pin.
This may cause malfunction or
permanent failure of this LSI.
I
Power-on reset This LSI enters the power-on reset
state when this signal goes low.
I
Manual reset This LSI enters the manual reset
state when this signal goes low.
WDTOVF O Watchdog timer Outputs an overflow signal from the
overflow
WDT.
BREQ
BACK
I
Bus-mastership A low level is input to this pin when
request
an external device requests the
release of the bus mastership.
O Bus-mastership Indicates that the bus mastership
request
has been released to an external
acknowledge device. Reception of the BACK
signal informs the device which has
output the BREQ signal that it has
acquired the bus.
Rev. 2.00 May. 08, 2008 Page 10 of 1200
REJ09B0344-0200