SH7211 Datasheet, PDF (371/1228 Pages) Renesas Technology Corp – 32-Bit RISC Microcomputer SuperHTM RISC engine Family

Figure 9.17 shows the TEND output timing.
Section 9 Direct Memory Access Controller (DMAC)
CK
Bus cycle
DREQ
DACK
DMAC
End of DMA transfer
CPU
DMAC
CPU
CPU
TEND
Figure 9.17 Example of DMA Transfer End Signal Timing
(Cycle Steal Mode Level Detection)
The unit of the DMA transfer is divided into multiple bus cycles when 16-byte transfer is
performed for an 8-bit or 16-bit external device, when longword access is performed for an 8-bit
or 16-bit external device, or when word access is performed for an 8-bit external device. When a
setting is made so that the DMA transfer size is divided into multiple bus cycles and the CS signal
is negated between bus cycles, note that DACK and TEND are divided like the CS signal for data
alignment. Also, if the DREQ detection is set to level-detection mode (DS bit in CHCR = 0), the
DREQ sampling may not be detected correctly with divided DACK, and one extra overrun may
occur at maximum.
Use a setting that does not divide DACK or specify a transfer size smaller than the external device
bus width if DACK is divided. Figure 9.18 shows this example.
Rev. 2.00 May. 08, 2008 Page 347 of 1200
REJ09B0344-0200