SH7211 Datasheet, PDF (1183/1228 Pages) Renesas Technology Corp – 32-Bit RISC Microcomputer SuperHTM RISC engine Family

Item
16.3.3 I²C Bus Mode
Register (ICMR)
Page
734
16.4.2 Master Transmit 745
Operation
16.6 Bit Synchronous 765
Circuit
Figure 16.22 Bit
Synchronous Circuit
Timing
Table 16.5 Time for 766
Monitoring SCL
Revision (See Manual for Details)
Figure amended
Bit: 7
6
5
4
3
2
1
0
MLS
-
-
- BCWP
BC[2:0]
Initial value: 0
0
1
1
1
0
0
0
R/W: R/W R
R
R R/W R/W R/W R/W
Table amended
Initial
Bit
Bit Name Value R/W
Description
6
—
0
R
Reserved
This bit is always read as 0. The write value should
always be 0.
Description amended
1. Set the ICE bit in ICCR1 to 1. Also, set the
in ICCR1. (Initial setting)
Figure replaced
bits CKS[3:0]
Table amended
CKS3
CKS2
Time for Monitoring SCL
0
0
9 tpcyc*
1
21 tpcyc*
1
0
33 tpcyc*
1
81 tpcyc*
Note: * tpcyc stands for the peripheral clock (Pφ) cycle.
16.7 Usage Notes
17.1 Features
767
Newly added
769
Description amended
• High-speed conversion
When Aφ = 40 MHz: Minimum 1.25 μs per channel
AD clock = 40 MHz, 50 conversion
states
• A/D data registers
Eight A/D data registers (ADDR) are provided. A/D
conversion results are stored in A/D data registers (ADDR)
that correspond to the input channels.
Rev. 2.00 May. 08, 2008 Page 1159 of 1200
REJ09B0344-0200