SH7211 Datasheet, PDF (1182/1228 Pages) Renesas Technology Corp – 32-Bit RISC Microcomputer SuperHTM RISC engine Family

Item
Page
15.4.3 Operation in
714
Clocked Synchronous
Mode
Figure 15.11 Sample
Flowchart for
Transmitting Serial Data
Figure 15.16 Sample 719
Flowchart for
Transmitting/Receiving
Serial Data
15.6.7 FER and PER 724
Flags in the Serial Status
Register (SCFSR)
16.3.1 I²C Bus Control 729
Register 1 (ICCR1)
Table 16.3 Transfer 731
Rate
Revision (See Manual for Details)
Figure amended
Start of transmission
Read TDFE flag in SCFSR
No
TDFE = 1?
Yes
Write transmit data to SCFTDR,
read TDFE and TEND flags in
SCFSR, and clear the TDRE and
[1]
TEND flags in SCFSR to 0
All data transmitted?
No
[2]
[1] SCIF status check and transmit data
write:
Read SCFSR and check that the
TDFE flag is set to 1, then write
transmit data to SCFTDR, read 1
from the TDFE and TEND flags, and
clear these flags to 0.
[2] Serial transmission continuation
procedeure:
To continue serial transmission, read
1 from the TDFE flag to confirm that
writing is possible, them write data to
SCFTDR, and then clear the TDFE
flag to 0.
Figure amended
Initialization
Start of transmission and reception
Read TDFE flag in SCFSR
No
TDFE = 1?
Yes
Write transmit data to SCFTDR,
read 1 from the TDFE and TEND
flags in SCFSR, and clear the TDFE ^[1]
and TEND flags in SCFSR to 0
Read ORER flag in SCLSR
Newly added
[1] SCIF status check and transmit data
write:
Read SCFSR and check that the
TDFE flag is set to 1, then write
transmit data to SCFTDR, read 1
from the TDFE and TEND flags, and
clear these flags to 0. The transition
of the TDFE flag from 0 to 1 can also
be identified by a TXI interrupt.
[2] Receive error handling:
Read the ORER flag in SCLSR to
identify any error, perform the
appropriate error handling, then clear
the ORER flag to 0. Reception cannot
be resumed while the ORER flag is
set to 1.
[3] SCIF status check and receive data
read:
Table amended
Initial
Bit
Bit Name Value R/W
6
RCVD
0
R/W
Table replaced
Description
Reception Disable
Enables or disables continuous reception when TRS =
0 and ICDRR is not read. If ICDRR cannot be read by
the rising of 8th clock cycle of SCL in master receive
mode, reception in byte units should be performed by
setting the RCVD bit to 1.
0: Enables continuous reception
1: Disables continuous reception
Rev. 2.00 May. 08, 2008 Page 1158 of 1200
REJ09B0344-0200