SH7211 Datasheet, PDF (285/1228 Pages) Renesas Technology Corp – 32-Bit RISC Microcomputer SuperHTM RISC engine Family

Section 8 Bus State Controller (BSC)
CK
A25 to A0
A12/A11*¹
CS3
RASL
CASL
RD/WR
DQMxx
D15 to D0
BS
DACKn*²
Td1
Td2
Td3
Td4
Tp
Tpw
Tr
Tc1
Tc2
Tc3
Tc4
Tde
Notes: 1. Address pin to be connected to pin A10 of SDRAM.
2. The waveform for DACKn is when active low is specified.
Figure 8.21 Burst Read Timing (Bank Active, Different Row Addresses in the Same Bank,
CAS Latency 1)
Rev. 2.00 May. 08, 2008 Page 261 of 1200
REJ09B0344-0200