SH7211 Datasheet, PDF (126/1228 Pages) Renesas Technology Corp – 32-Bit RISC Microcomputer SuperHTM RISC engine Family

Section 6 Interrupt Controller (INTC)
Figure 6.1 shows a block diagram of the INTC.
IRQOUT
NMI
IRQ7 to IRQ0
Input control
UBC
H-UDI
DMAC
CMT
BSC
WDT
MTU2
MTU2S
POE2
ADC
IIC3
SCIF
WAVEIF
(Interrupt request)
(Interrupt request)
(Interrupt request)
(Interrupt request)
(Interrupt request)
(Interrupt request)
(Interrupt request)
(Interrupt request)
(Interrupt request)
(Interrupt request)
(Interrupt request)
(Interrupt request)
(Interrupt request)
CPU/
DMAC
interrupt
requests
identifier
Priority
identifier
Com-
parator
Interrupt
request
SR
I3 I2 I1 I0
CPU
ICR0
IBCR
ICR1
IRQRR
IBNR
IPR
IPR01, IPR02,
IPR05 to IPR15
Module bus
Bus
interface
[Legend]
UBC: User break controller
H-UDI: User debugging interface
DMAC: Direct memory access controller
CMT: Compare match timer
BSC: Bus state controller
WDT: Watchdog timer
MTU2: Multi-function timer pulse unit 2
MTU2S: Multi-function timer pulse unit 2S
POE2: Port output enable 2
ADC: A/D converter
IIC3: I²C bus interface 3
SCIF: Serial communication interface with FIFO
WAVEIF: WAVE interface
INTC
ICR0:
Interrupt control register 0
ICR1:
Interrupt control register 1
IRQRR:
IRQ interrupt request register
IBCR:
Bank control register
IBNR:
Bank number register
IPR01, 02, 05 to 15: Interrupt priority registers 01, 02,
05 to 15
Figure 6.1 Block Diagram of INTC
Rev. 2.00 May. 08, 2008 Page 102 of 1200
REJ09B0344-0200