SH7211 Datasheet, PDF (569/1228 Pages) Renesas Technology Corp – 32-Bit RISC Microcomputer SuperHTM RISC engine Family

Section 10 Multi-Function Timer Pulse Unit 2 (MTU2)
Pφ
TCNTS P − 1
P
H'0000
Buffer transfer
signal
Temporary
register
N
Compare
register
n
N
Figure 10.108 Transfer Timing from Temporary Register to Compare Register
10.6.2 Interrupt Signal Timing
(1) TGF Flag Setting Timing in Case of Compare Match
Figures 10.109 and 110 show the timing for setting of the TGF flag in TSR on compare match,
and TGI interrupt request signal timing.
Pφ
TCNT input
clock
TCNT
N
N+1
TGR
N
Compare
match signal
TGF flag
TGI interrupt
Figure 10.109 TGI Interrupt Timing (Compare Match)
Rev. 2.00 May. 08, 2008 Page 545 of 1200
REJ09B0344-0200