SH7211 Datasheet, PDF (253/1228 Pages) Renesas Technology Corp – 32-Bit RISC Microcomputer SuperHTM RISC engine Family

Section 8 Bus State Controller (BSC)
8.5 Operation
8.5.1 Endian/Access Size and Data Alignment
This LSI supports big endian in which the 0 address is the most significant byte (MSB), and little
endian in which the 0 address is the least significant byte (LSB) in the byte data. In a space of
areas 1 to 7, endian can be set by the CSnBCR setting while the target space is not accessed. In a
space of area 0, the CSnBCR setting is invalid in on-chip ROM-disabled mode. In on-chip ROM-
enabled mode, endian can be set by the CSnBCR setting in a space of areas 0 to 7.
Two data bus widths (8 bits and 16 bits) are available for normal memory and SRAM with byte
selection. Only 16-bit data bus width is available for SDRAM. For MPX-I/O, the data bus width is
fixed at 8 bits or 16 bits, or 8 bits or 16 bits can be selected by the access address. Data alignment
is performed in accordance with the data bus width of the device. This also means that when
longword data is read from a byte-width device, the read operation must be done four times. In
this LSI, data alignment and conversion of data length is performed automatically between the
respective interfaces.
Tables 8.5 to 8.8 show the relationship between device data width and access unit. Note that
addresses corresponding to the strobe signals for the 16-bit bus width differ between big endian
and little endian. WE1 indicates the 0 address in big-endian mode, but WE0 indicates the 0
address in little-endian mode.
Table 8.5 16-Bit External Device Access and Data Alignment in Big-Endian Mode
Data Bus
Operation
D15 to D8
D7 to D0
Byte access at 0
Data 7 to 0
⎯
Byte access at 1
⎯
Data 7 to 0
Byte access at 2
Data 7 to 0
⎯
Byte access at 3
⎯
Data 7 to 0
Word access at 0
Data 15 to 8
Data 7 to 0
Word access at 2
Data 15 to 8
Data 7 to 0
Longword
access at 0
1st time at 0 Data 23 to 16
2nd time at 2 Data 7 to 0
Data 31 to 24
Data 15 to 8
Strobe Signals
WE1, DQMLU WE0, DQMLL
Assert
⎯
⎯
Assert
Assert
⎯
⎯
Assert
Assert
Assert
Assert
Assert
Assert
Assert
Assert
Assert
Rev. 2.00 May. 08, 2008 Page 229 of 1200
REJ09B0344-0200