SH7211 Datasheet, PDF (192/1228 Pages) Renesas Technology Corp – 32-Bit RISC Microcomputer SuperHTM RISC engine Family

Section 7 User Break Controller (UBC)
7.4.3 Break on Data Access Cycle
1. If the C bus is specified as a break condition for data access break, condition comparison is
performed for the virtual address accessed by the executed instructions, and a break occurs if
the condition is satisfied. If the I bus is specified as a break condition, condition comparison is
performed for the physical address of the data access cycles that are issued by the bus master
specified by the bits to select the bus master of the I bus, and a break occurs if the condition is
satisfied. For details on the CPU bus cycles issued on the I bus, see 6 in section 7.4.1, Flow of
the User Break Operation.
2. The relationship between the data access cycle address and the comparison condition for each
operand size is listed in table 7.3.
Table 7.3 Data Access Cycle Addresses and Operand Size Comparison Conditions
Access Size
Longword
Word
Byte
Address Compared
Compares break address register bits 31 to 2 to address bus bits 31 to 2
Compares break address register bits 31 to 1 to address bus bits 31 to 1
Compares break address register bits 31 to 0 to address bus bits 31 to 0
This means that when address H'00001003 is set in the break address register (BAR), for
example, the bus cycle in which the break condition is satisfied is as follows (where other
conditions are met).
Longword access at H'00001000
Word access at H'00001002
Byte access at H'00001003
3. If the data access cycle is selected, the instruction at which the break will occur cannot be
determined.
Rev. 2.00 May. 08, 2008 Page 168 of 1200
REJ09B0344-0200