SH7211 Datasheet, PDF (1174/1228 Pages) Renesas Technology Corp – 32-Bit RISC Microcomputer SuperHTM RISC engine Family

Item
5.3.1 Address Error
Sources
Table 5.6 Bus Cycles
and Address Errors
Page
87
5.3.2 Address Error 88
Exception Handling
6.3.4 IRQ Interrupt
110
Request Register
(IRQRR)
Revision (See Manual for Details)
Table amended
Bus Cycle
Type
Bus
Master
Instruction
fetch
CPU
Data
read/write
CPU or
DMAC
Bus Cycle Description
Instruction fetched from even address
Instruction fetched from odd address
Instruction fetched from other than on-chip
peripheral module space* or H'F0000000 to
H'F5FFFFFF in on-chip RAM space*
Instruction fetched from on-chip peripheral
module space* or H'F0000000 to
H'F5FFFFFF in on-chip RAM space*
Instruction fetched from external memory
space in single-chip mode
Word data accessed from even address
Word data accessed from odd address
Longword data accessed from a longword
boundary
Longword data accessed from other than a
long-word boundary
Byte or word data accessed in on-chip
peripheral module space*
Longword data accessed in 16-bit on-chip
peripheral module space*
Longword data accessed in 8-bit on-chip
peripheral module space*
Instruction fetched from external memory
space in single-chip mode
Address Errors
None (normal)
Address error occurs
None (normal)
Address error occurs
Address error occurs
None (normal)
Address error occurs
None (normal)
Address error occurs
None (normal)
None (normal)
None (normal)
Address error occurs
Note added
When an address error occurs, the bus cycle in which the
address error occurred ends*. When the executing instruction
then finishes, address error exception handling starts. The
CPU operates as follows:
Note: * This is the case in which an address error was
caused by data read or write. When an address error
is caused by an instruction fetch, and if the bus cycle
in which the address error occurred does not end by
step 3 above, the CPU restarts the address error
exception handling until the bus cycle ends.
Note added
Note: * Only 0 can be written to clear the flag after 1 is read.
Rev. 2.00 May. 08, 2008 Page 1150 of 1200
REJ09B0344-0200