SH7211 Datasheet, PDF (659/1228 Pages) Renesas Technology Corp – 32-Bit RISC Microcomputer SuperHTM RISC engine Family

Section 12 Port Output Enable 2 (POE2)
12.6 Usage Note
12.6.1 Pin Status When the WDT Issues a Power-On Reset
When a power-on reset is issued by the WDT, the pin function controller (PFC) is initialized and
the I/O ports function as general inputs (initial value).
If a power-on reset is issued by the WDT during high-impedance processing by the port output
enable (POE) signal, the I/O port pins are placed in output state for a time period of one cycle of
the peripheral clock, Pφ, until the pin functions switch to general inputs.
If a power-on reset is issued by the WDT during high-impedance processing by MTU2 or MTU2S
short detection, the I/O port pins are placed in the same status as described above.
Figure 12.5 shows the I/O port pin status when a power-on reset is issued by the WDT during
high-impedance processing by the POE input while the timer output is selected.
Pφ
POE input
Pin status
Timer output
PFC setting value
Timer output
High-impedance state
Timer
output
General input
One cycle of the
peripheral clock Pφ
General input
Power-on reset by WDT
Figure 12.5 Pin Status When Power-on Reset is Issued from Watchdog Timer
Rev. 2.00 May. 08, 2008 Page 635 of 1200
REJ09B0344-0200