SH7211 Datasheet, PDF (1167/1228 Pages) Renesas Technology Corp – 32-Bit RISC Microcomputer SuperHTM RISC engine Family

Appendix
Notes: 1. Controlled by the HIZ bit in standby control register 3 (STBCR3) (see section 23,
Power-Down Modes).
2. Controlled by the HIZCNT bit in the common control register of the BSC (see section 8,
Bus State Controller (BSC)).
3. Controlled by the HIZMEM bit in the common control register of the BSC (see section 8,
Bus State Controller (BSC)).
4. Controlled by the HIZCKIO bit in the common control register of the BSC (see section 8,
Bus State Controller (BSC)).
5. Z when the TAP controller of the H-UDI is neither the Shift-DR nor Shift-IR state.
6. High-impedance control through POE2 (see section 12, Port Output Enable 2 (POE2)).
7. Power-on reset by low-level input to the RES pin. The pin states after a power-on reset
by the H-UDI reset assert command or WDT overflow are the same as the initial pin
states at normal operation (see section 19, Pin Function Controller (PFC)).
Rev. 2.00 May. 08, 2008 Page 1143 of 1200
REJ09B0344-0200