SH7211 Datasheet, PDF (578/1228 Pages) Renesas Technology Corp – 32-Bit RISC Microcomputer SuperHTM RISC engine Family

Section 10 Multi-Function Timer Pulse Unit 2 (MTU2)
10.7.7 Contention between Buffer Register Write and Compare Match
If a compare match occurs in the T2 state of a TGR write cycle, the data that is transferred to TGR
by the buffer operation is the data after write.
Figure 10.122 shows the timing in this case.
Pφ
Address
Write signal
Compare match
signal
Compare match
buffer signal
Buffer register
TGR write cycle
T1
T2
Buffer register
address
Buffer register write data
N
M
TGR
N
Figure 10.122 Contention between Buffer Register Write and Compare Match
Rev. 2.00 May. 08, 2008 Page 554 of 1200
REJ09B0344-0200