SH7211 Datasheet, PDF (1012/1228 Pages) Renesas Technology Corp – 32-Bit RISC Microcomputer SuperHTM RISC engine Family

Section 22 On-Chip RAM
22.2 Usage Notes
22.2.1 Page Conflict
When the same page is accessed from different buses simultaneously, a conflict on the page
occurs. Although each access is completed correctly, this kind of conflict degrades the memory
access speed. Therefore, it is advisable to provide software measures to prevent such conflicts as
far as possible. For example, no conflict will arise if different memory or pages are accessed by
each bus.
22.2.2 RAME and RAMWE Bits
Before disabling memory operation or write access through the RAME or RAMWE bit, be sure to
read from any address and then write to the same address in each page; otherwise, the last written
data in each page may not be actually written to the RAM. For setting the RAME and RAMWE
bits, see section 23.3.5, System Control Register 1 (SYSCR1), and section 23.3.6, System Control
Register 2 (SYSCR2).
Rev. 2.00 May. 08, 2008 Page 988 of 1200
REJ09B0344-0200