SH7211 Datasheet, PDF (672/1228 Pages) Renesas Technology Corp – 32-Bit RISC Microcomputer SuperHTM RISC engine Family

Section 13 Compare Match Timer (CMT)
13.5.3 Conflict between Byte-Write and Count-Up Processes of CMCNT
Even when the count-up occurs in the T2 cycle while writing to CMCNT in bytes, the writing has
priority over the count-up. In this case, the count-up is not performed. The byte data on the other
side, which is not written to, is also not counted and the previous contents are retained.
Figure 13.7 shows the timing when the count-up occurs in the T2 cycle while writing to
CMCNTH in bytes.
Peripheral clock
(Pφ)
Address signal
Internal write signal
CMCNT count-up
enable signal
CMCNTH
CMCSR write cycle
T1
T2
CMCNTH
N
M
CMCNTL
X
X
Figure 13.7 Conflict between Byte-Write and Count-Up Processes of CMCNT
13.5.4 Compare Match Between CMCNT and CMCOR
Do not set a same value to CMCNT and CMCOR while the count operation of CMCNT is
stopped.
Rev. 2.00 May. 08, 2008 Page 648 of 1200
REJ09B0344-0200