SH7211 Datasheet, PDF (321/1228 Pages) Renesas Technology Corp – 32-Bit RISC Microcomputer SuperHTM RISC engine Family

Section 8 Bus State Controller (BSC)
peripheral bus (the example in figure 8.41 is for 4 × Bφ). Therefore, when Bφ:Pφ is 4:1, data is
transferred from the I bus to the peripheral bus in time (1+m) × Bφ, where m = 0 to 3 periods.
Note that the relationship between the timing with which the data appears on the I bus and the Pφ
rising edge depends on the program execution state. In figure 8.41, since n = 0 and m = 3, the
access time will be 2 × Iφ + 4 × Bφ + 2 × Pφ.
Iφ
C bus
Bφ
I bus
Pφ
Peripheral bus
(2+n) × Iφ
(1+m) × Bφ
2 × Pφ
Figure 8.41 Internal Peripheral I/O Register Timing when Iφ:Bφ:Pφ = 4:4:1
Figure 8.42 shows an example of the write timing to the peripheral bus when the relationship
between the clocks is Iφ:Bφ:Pφ = 4:2:1. Although transfers from the C bus to the peripheral bus
are performed the same way for write, for read, the value read from the peripheral bus must be
transferred to the CPU. Although the transfers from the peripheral bus to the I bus and from the I
bus to the C bus are all performed on the corresponding bus clock rising edge, since Iφ ≥ Bφ ≥ Pφ,
(2 + 1) × Iφ periods are actually required. In the example in figure 8.42, since n = 1, m = 1, and i =
1, the access period will be 3 × Iφ + 2 × Bφ + 2 × Pφ + 3 × Iφ.
Iφ
C bus
Bφ
I bus
Pφ
Peripheral bus
(2+n) × Iφ
(1+m) × Bφ
2 × Pφ
(2+I) × Iφ
Figure 8.42 Internal Peripheral I/O Register Timing when Iφ:Bφ:Pφ = 4:2:1
Rev. 2.00 May. 08, 2008 Page 297 of 1200
REJ09B0344-0200