SH7211 Datasheet, PDF (1180/1228 Pages) Renesas Technology Corp – 32-Bit RISC Microcomputer SuperHTM RISC engine Family

Item
15.1 Features
Page
666
Revision (See Manual for Details)
Description deleted
• When the SCIF is not in use, it can be stopped by halting
the clock supplied to it, saving power.
15.3.7 Serial Status 682
Register (SCFSR)
15.3.8 Bit Rate Register 687
(SCBRR)
• The quantity of data in the transmit and receive FIFO data
registers and the number of receive errors of the receive
data in the receive FIFO data register can be ascertained.
Table amended
Initial
Bit
Bit Name Value R/W
Description
5
TDFE
1
R/(W)*
Transmit FIFO Data Empty
Indicates that data has been transferred from the
transmit FIFO data register (SCFTDR) to the transmit
shift register (SCTSR), the quantity of data in
SCFTDR has become less than the transmission
trigger number specified by the TTRG1 and TTRG0
bits in the FIFO control register (SCFCR), and writing
of transmit data to SCFTDR is enabled.
0: The quantity of transmit data written to SCFTDR is
greater than the specified transmission trigger
number
[Clearing conditions]
• TDFE is cleared to 0 when data exceeding the
specified transmission trigger number is written to
SCFTDR after 1 is read from TDFE and then 0 is
written
• TDFE is cleared to 0 when data exceeding the
specified transmission trigger number is written to
SCFTDR by the DMAC.
1: The quantity of transmit data in SCFTDR is equal
to or less than the specified transmission trigger
number*
[Setting conditions]
• TDFE is set to 1 by a power-on reset
• TDFE is set to 1 when the quantity of transmit
data in SCFTDR becomes equal to or less than
the specified transmission trigger number as a
result of transmission.
Note: * Since SCFTDR is a 16-byte FIFO register,
the maximum quantity of data that can be
written when TDFE is 1 is "16 minus the
specified transmission trigger number". If an
attempt is made to write additional data, the
data is ignored. The quantity of data in
SCFTDR is indicated by the upper 8 bits of
SCFDR.
Description amended
The CPU can always read and write to SCBRR. SCBRR is
initialized to H'FF by a power-on reset. Each channel has
independent baud rate generator control, so different values
can be set in four channels.
Rev. 2.00 May. 08, 2008 Page 1156 of 1200
REJ09B0344-0200