SH7211 Datasheet, PDF (1128/1228 Pages) Renesas Technology Corp – 32-Bit RISC Microcomputer SuperHTM RISC engine Family

Section 27 Electrical Characteristics
Th
T1
Twx
T2
Tf
CK
t_AD1
t_AD1
A25 to A0
t_CSD1
t_CSD1
CSn
WEn
t_RWD1
t_WED1
t_WED1
t_RWD1
RD/WR
Read
RD
D15 to D0
tRSD
t_RSD
t_RDS1
t_RDH1
Write
RD/WR
tRWD1
t_WDD1
t_RWD1
t_WDH1
D15 to D0
BS
DACKn
TENDn*
t_BSD
t_DACD
t_BSD
t_WTH
t_WTH
t_DACD
WAIT
t_WTS
tWTS
Note: * The waveform for DACKn and TENDn is when active low is specified.
Figure 27.17 Bus Cycle of SRAM with Byte Selection (SW = 1 Cycle, HW = 1 Cycle,
One Asynchronous External Wait Cycle, BAS = 0 (Write Cycle UB/LB Control))
Rev. 2.00 May. 08, 2008 Page 1104 of 1200
REJ09B0344-0200