SH7211 Datasheet, PDF (331/1228 Pages) Renesas Technology Corp – 32-Bit RISC Microcomputer SuperHTM RISC engine Family

Section 9 Direct Memory Access Controller (DMAC)
Channel Register Name
Abbreviation R/W Initial Value Address
Access
Size
Common DMA operation register DMAOR
R/W*² H'0000
H'FFFE1200 8, 16
0 and 1 DMA extension
resource selector 0
DMARS0
R/W H'0000
H'FFFE1300 16
2 and 3 DMA extension
resource selector 1
DMARS1
R/W H'0000
H'FFFE1304 16
4 and 5 DMA extension
resource selector 2
DMARS2
R/W H'0000
H'FFFE1308 16
6 and 7 DMA extension
resource selector 3
DMARS3
R/W H'0000
H'FFFE130C 16
Notes: 1. For the HE and TE bits in CHCRn, only 0 can be written to clear the flags after 1 is
read.
2. For the AE and NMIF bits in DMAOR, only 0 can be written to clear the flags after 1 is
read.
9.3.1 DMA Source Address Registers (SAR)
The DMA source address registers (SAR) are 32-bit readable/writable registers that specify the
source address of a DMA transfer. During a DMA transfer, these registers indicate the next source
address. When the data of an external device with DACK is transferred in single address mode,
SAR is ignored.
To transfer data of 16-bit or 32-bit width, specify the address with 16-bit or 32-bit address
boundary respectively. To transfer data in units of 16 bytes, set a value at a 16-byte boundary.
SAR is initialized to H'00000000 by a reset and retains the value in software standby mode and
module standby mode.
Bit: 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
Initial value: 0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
R/W: R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W
Bit: 15 14 13 12 11 10 9
8
7
6
5
4
3
2
1
0
Initial value: 0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
R/W: R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W
Rev. 2.00 May. 08, 2008 Page 307 of 1200
REJ09B0344-0200