SH7211 Datasheet, PDF (806/1228 Pages) Renesas Technology Corp – 32-Bit RISC Microcomputer SuperHTM RISC engine Family

Section 17 A/D Converter (ADC)
5. When A/D conversion ends on all specified channels (AN0 to AN3), the ADF bit is set to 1,
the ADST bit is automatically cleared to 0, and the A/D conversion ends. At this time, if the
ADIE bit is set to 1, an ADI interrupt is generated after the A/D conversion.
A/D conversion execution
ADST
ADST set
ADST automatically cleared
ADF
AN0
AN1
AN2
ADF cleared
Simultaneous sampling
Waiting for
conversion
S
OFC
H
A/D
conversion
Simultaneous sampling
Waiting for
conversion
S
OFC
H
H
A/D
conversion
Simultaneous sampling
Waiting for
conversion
S
OFC
H
H
A/D
conversion
Waiting for conversion
Waiting for conversion
Waiting for conversion
AN3
Waiting for
conversion
OFC
Waiting for conversion
A/D
conversion
Waiting for conversion
ADDR0
A/D conversion result (AN0)
ADDR1
A/D conversion result (AN1)
ADDR2
A/D conversion result (AN2)
ADDR3
A/D conversion result (AN3)
[Legend]
OFC: Offset canceling processing
S: Sampling
H: Holding
Figure 17.2 Example of A/D_0 Converter Operation (Single-Cycle Scan Mode)
Rev. 2.00 May. 08, 2008 Page 782 of 1200
REJ09B0344-0200