SH7211 Datasheet, PDF (344/1228 Pages) Renesas Technology Corp – 32-Bit RISC Microcomputer SuperHTM RISC engine Family

Section 9 Direct Memory Access Controller (DMAC)
9.3.7 DMA Reload Transfer Count Registers (RDMATCR)
The DMA reload transfer count registers (RDMATCR) are 32-bit readable/writable registers.
When the reload function is enabled, the RDMATCR value is written to the transfer count register
(DMATCR) at the end of the current DMA transfer. In this case, a new value for the next DMA
transfer can be preset in RDMATCR during the current DMA transfer. When the reload function
is disabled, RDMATCR is ignored.
The upper eight bits of RDMATCR are always read as 0, and the write value should always be 0.
As in DMATCR, the transfer count is 1 when the setting is H'00000001, 16,777,215 when
H'00FFFFFF is set, and 16,777,216 (the maximum) when H'00000000 is set. To transfer data in
16 bytes, one 16-byte transfer (128 bits) counts one.
RDMATCR is initialized to H'00000000 by a reset and retains the value in software standby mode
and module standby mode.
Bit: 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
-
-
-
-
-
-
-
-
Initial value: 0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
R/W: R
R
R
R
R
R
R
R R/W R/W R/W R/W R/W R/W R/W R/W
Bit: 15 14 13 12 11 10 9
8
7
6
5
4
3
2
1
0
Initial value: 0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
R/W: R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W
Rev. 2.00 May. 08, 2008 Page 320 of 1200
REJ09B0344-0200