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SH7211 Datasheet, PDF (58/1228 Pages) Renesas Technology Corp – 32-Bit RISC Microcomputer SuperHTM RISC engine Family | |||
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Section 2 CPU
Instruction Formats
i format
15
0
xxxx xxxx iiii iiii
ni format
15
xxxx nnnn
0
iiii iiii
ni3 format
15
0
xxxx xxxx nnnn x iii
Source
Operand
iiiiiiii: Immediate
iiiiiiii: Immediate
iiiiiiii: Immediate
iiiiiiii: Immediate
Destination
Operand
Example
Indexed GBR
indirect
AND.B
#imm,@(R0,GBR)
R0 (Register direct) AND #imm,R0
â
TRAPA #imm
nnnn: Register direct ADD #imm,Rn
nnnn: Register direct â
BLD
iii: Immediate
â
nnnn: Register direct BST
iii: Immediate
#imm3,Rn
#imm3,Rn
ni20 format
32
16
xxxx nnnn iiii xxxx
iiiiiiiiiiiiiiiiiiii:
Immediate
nnnn: Register direct MOVI20
#imm20, Rn
15
0
iiii iiii iiii iiii
nid format
32
16
xxxx nnnn xiii xxxx
nnnndddddddddddd: â
Register indirect with
displacement
BLD.B
#imm3,@(disp12,Rn)
15
0
xxxx dddd dddd dddd
iii: Immediate
â
nnnndddddddddddd: BST.B
Register indirect with #imm3,@(disp12,Rn)
displacement
iii: Immediate
Note: * In multiply-and-accumulate instructions, nnnn is the source register.
Rev. 2.00 May. 08, 2008 Page 34 of 1200
REJ09B0344-0200
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