SH7211 Datasheet, PDF (655/1228 Pages) Renesas Technology Corp – 32-Bit RISC Microcomputer SuperHTM RISC engine Family

Section 12 Port Output Enable 2 (POE2)
12.4.1 Input Level Detection Operation
If the input conditions set by ICSR1 to ICSR3 occur on the POE0, POE1, POE3, POE4, POE7,
and POE8 pins, the high-current pins and the pins for channel 0 of the MTU2 are placed in high-
impedance state. Note however, that these high-current and MTU2 pins enter high-impedance
state only when general input/output function, MTU2 function, or MTU2S function is selected for
these pins.
(1) Falling Edge Detection
When a change from a high to low level is input to the POE0, POE1, POE3, POE4, POE7, and
POE8 pins, the high-current pins and the pins for channel 0 of the MTU2 are placed in high-
impedance state.
Figure 12.2 shows the sample timing after the level changes in input to the POE0, POE1, POE3,
POE4, POE7, and POE8 pins until the respective pins enter high-impedance state.
Pφ
POE input
PB18/
TIOC3B
Pφ rising edge
Falling edge detection
High-impedance state
Note: The other high-current pins and MTU2 channel 0 pins also enter the high-impedance state in the similar timing.
Figure 12.2 Falling Edge Detection
Rev. 2.00 May. 08, 2008 Page 631 of 1200
REJ09B0344-0200