SH7211 Datasheet, PDF (690/1228 Pages) Renesas Technology Corp – 32-Bit RISC Microcomputer SuperHTM RISC engine Family

Section 15 Serial Communication Interface with FIFO (SCIF)
• Four types of interrupts: Transmit-FIFO-data-empty interrupt, break interrupt, receive-FIFO-
data-full interrupt, and receive-error interrupts are requested independently.
• When the SCIF is not in use, it can be stopped by halting the clock supplied to it, saving
power.
• The quantity of data in the transmit and receive FIFO data registers and the number of receive
errors of the receive data in the receive FIFO data register can be ascertained.
• A time-out error (DR) can be detected when receiving in asynchronous mode.
Figure 15.1 shows a block diagram of the SCIF.
Module data bus
RXD
TXD
SCK
SCFRDR (16 stage)
SCRSR
SCFTDR (16 stage)
SCSMR
SCBRR
SCLSR
SCFDR
SCTSR
SCFCR
SCFSR
SCSCR
Baud rate
generator
SCSPTR
SCSEMR
Transmission/reception
control
Parity generation
Clock
Parity check
External clock
[Legend]
SCRSR:
SCFRDR:
SCTSR:
SCFTDR:
SCSMR:
SCSCR:
Receive shift register
Receive FIFO data register
Transmit shift register
Transmit FIFO data register
Serial mode register
Serial control register
SCIF
SCFSR:
SCBRR:
SCSPTR:
SCFCR:
SCFDR:
SCLSR:
SCSEMR:
Serial status register
Bit rate register
Serial port register
FIFO control register
FIFO data count register
Line status register
Serial extended mode register
Figure 15.1 Block Diagram of SCIF
Internal
data bus
Pφ
Pφ/4
Pφ/16
Pφ/64
TXI
RXI
ERI
BRI
Rev. 2.00 May. 08, 2008 Page 666 of 1200
REJ09B0344-0200