SH7211 Datasheet, PDF (1173/1228 Pages) Renesas Technology Corp – 32-Bit RISC Microcomputer SuperHTM RISC engine Family

Item
4.4.1 Frequency
Control Register
(FRQCR)
Page
70
5.2.2 Power-On Reset 84
(1) Power-On Reset by
Means of RES Pin
5.2.3 Manual Reset 86
(1) Manual Reset by
Means of MRES Pin
Revision (See Manual for Details)
Table amended
Bit
6 to 4
Initial
Bit Name Value
IFC[2:0] 000
R/W
R/W
Description
Internal Clock (Iφ) Frequency Division Ratio
These bits specify the frequency division ratio of the
internal clock with respect to the output frequency of
PLL circuit 1.
If a prohibited value is specified, correct operation
cannot be guaranteed.
000: × 1 time
001: × 1/2 time
011: × 1/4 time
Other than above: Setting prohibited
2 to 0 PFC[2:0] 011
R/W Peripheral Clock (Pφ) Frequency Division Ratio
These bits specify the frequency division ratio of the
peripheral clock with respect to the output frequency
of PLL circuit 1.
If a prohibited value is specified, correct operation
cannot be guaranteed.
000: × 1 time
001: × 1/2 time
011: × 1/4 time
101: × 1/8 time
Other than above: Setting prohibited
Description amended
When the RES pin is driven low, this LSI enters the power-on
reset state. To reliably reset this LSI, the RES pin should be
kept at the low level for the duration of the oscillation settling
time at power-on or when in software standby mode (when the
clock is halted), or at least 20-tcyc when the clock is
running.
Description amended
When the MRES pin is driven low, this LSI enters the manual
reset state. To reset this LSI without fail, the MRES pin should
be kept at the low level for at least 20-tcyc .
Rev. 2.00 May. 08, 2008 Page 1149 of 1200
REJ09B0344-0200