SH7211 Datasheet, PDF (809/1228 Pages) Renesas Technology Corp – 32-Bit RISC Microcomputer SuperHTM RISC engine Family

Section 17 A/D Converter (ADC)
17.4.3 Input Sampling and A/D Conversion Time
The A/D converter has a built-in sample-and-hold circuit common to all the channels. Each of
channels 0 to 2 of the A/D converter has a dedicated built-in sample-and-hold circuit. Channels 0
to 2 can be simultaneously sampled as one group. This group is referred to as Group A (GrA) (in
table 17.5). Even when only one channel is selected in the group by ADANSR, the sample-and-
hold operation is performed with the dedicated sample-and-hold circuit. When only the channels
without a dedicated sample-and-hold circuit are specified by ADANSR, the time that elapses is the
same as when a dedicated sample-and-hold circuit is used.
When an event that sets the ADST bit, for example, writing to this bit by the CPU, A/D converter
activation request from the MTU2, the MTU2S, or an external trigger signal occurs, the analog
input is sampled by the dedicated sample-and-hold circuit for each channel after the A/D
conversion start delay time (t_D) has passed and the offset canceling processing (OFC) is
performed. After this, the sampling of the analog input using the sample-and-hold circuit common
to all the channels is performed and then the A/D conversion is started. Figure 17.4 shows the A/D
conversion timing in this case. This A/D conversion time (t_CONV) includes the t_D, the offset
canceling processing time (t_OFC), the analog input sampling time with a dedicated sample-and-hold
circuit for each channel (t_SPLSH), and the analog input sampling time with the sample-and-hold
circuit common to all the channels (t_SPL). The t_SPLSH does not depend on the number of channels
simultaneously sampled.
In continuous scan mode, the A/D conversion time (t_CONV) given in table 17.6 applies to the
conversion time of the first cycle. The conversion time of the second and subsequent cycles is
expressed as (t_CONV − t_D + 6).
Table 17.5 Correspondence between Analog Input Channels and Groups being Allowed
Simultaneous Sampling
Analog Input Channels
AN0
AN1
AN2
AN3
AN4
AN5
AN6
AN7
Group
GrA
⎯
⎯
⎯
⎯
⎯
Rev. 2.00 May. 08, 2008 Page 785 of 1200
REJ09B0344-0200