SH7211 Datasheet, PDF (1193/1228 Pages) Renesas Technology Corp – 32-Bit RISC Microcomputer SuperHTM RISC engine Family

Item
22.2.2 RAME and
RAMWE Bits
Figure 22.1 Examples
of Read/Write before
Disabling RAM
Page
989
Revision (See Manual for Details)
Figure amended
// For page 1
MOV.L #H'FFF82000,R0
MOV.L @R0,R1
MOV.L R1,@R0
// For page 2
MOV.L #H'FFF84000,R0
MOV.L @R0,R1
MOV.L R1,@R0
24.3.2 Instruction
Register (SDIR)
26.2 Register Bits
1014
1037
// For page 3
MOV.L #H'FFF86000,R0
MOV.L @R0,R1
MOV.L R1,@R0
Note added
Note: * The initial value of the TI[7:0] bits is a reserved value.
When setting a command, the TI[7:0] bits must be
set to another value.
Table amended
Module Register
Bit
Bit
Bit
Bit
Bit
Bit
Bit
Bit
Name Abbreviation 31/23/15/7 30/22/14/6 29/21/13/5 28/20/12/4 27/19/11/3 26/18/10/2 25/17/9/1 24/16/8/0
INTC
IPR01
IRQ0[3:0]
IRQ1[3:0]
IRQ2[3:0]
IRQ3[3:0]
IPR02
IRQ4[3:0]
IRQ5[3:0]
IPR05
IRQ6[3:0]
IRQ7[3:0]
⎯
⎯
⎯
⎯
⎯
⎯
⎯
⎯
ADI[3:0]
⎯
⎯
⎯
⎯
IPR06
DMAC0[3:0]
DMAC1[3:0]
DMAC2[3:0]
DMAC3[3:0]
IPR07
DMAC4[3:0]
DMAC5[3:0]
DMAC6[3:0]
DMAC7[3:0]
IPR08
CMT0[3:0]
CMT1[3:0]
BSC[3:0]
WDT[3:0]
IPR09
MTU0(TGI0A to TGI0D)[3:0]
MTU0(TCI0V, TGI0E, TGI0F)[3:0]
MTU1(TGI1A, TGI1B)[3:0]
MTU1(TCI1V, TCI1U)[3:0]
Rev. 2.00 May. 08, 2008 Page 1169 of 1200
REJ09B0344-0200