SH7211 Datasheet, PDF (332/1228 Pages) Renesas Technology Corp – 32-Bit RISC Microcomputer SuperHTM RISC engine Family

Section 9 Direct Memory Access Controller (DMAC)
9.3.2 DMA Destination Address Registers (DAR)
The DMA destination address registers (DAR) are 32-bit readable/writable registers that specify
the destination address of a DMA transfer. During a DMA transfer, these registers indicate the
next destination address. When the data of an external device with DACK is transferred in single
address mode, DAR is ignored.
To transfer data of 16-bit or 32-bit width, specify the address with 16-bit or 32-bit address
boundary respectively. To transfer data in units of 16 bytes, set a value at a 16-byte boundary.
DAR is initialized to H'00000000 by a reset and retains the value in software standby mode and
module standby mode.
Bit: 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
Initial value: 0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
R/W: R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W
Bit: 15 14 13 12 11 10 9
8
7
6
5
4
3
2
1
0
Initial value: 0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
R/W: R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W
Rev. 2.00 May. 08, 2008 Page 308 of 1200
REJ09B0344-0200