SH7211 Datasheet, PDF (1019/1228 Pages) Renesas Technology Corp – 32-Bit RISC Microcomputer SuperHTM RISC engine Family

Section 23 Power-Down Modes
23.3.1 Standby Control Register (STBCR)
STBCR is an 8-bit readable/writable register that specifies the state of the power-down mode. This
register is initialized to H'00 by a power-on reset but retains its previous value by a manual reset
or in software standby mode. Only byte access is possible.
Bit: 7
6
5
4
3
2
1
0
STBY -
-
-
-
-
-
-
Initial value: 0
0
0
0
0
0
0
0
R/W: R/W R
R
R
R
R
R
R
Initial
Bit
Bit Name Value R/W
7
STBY
0
R/W
6 to 0 ⎯
All 0
R
Description
Software Standby
Specifies transition to software standby mode.
0: Executing SLEEP instruction puts chip into sleep
mode.
1: Executing SLEEP instruction puts chip into
software standby mode.
Reserved
These bits are always read as 0. The write value
should always be 0.
Rev. 2.00 May. 08, 2008 Page 995 of 1200
REJ09B0344-0200