SH7211 Datasheet, PDF (686/1228 Pages) Renesas Technology Corp – 32-Bit RISC Microcomputer SuperHTM RISC engine Family

Section 14 Watchdog Timer (WDT)
14.4.4 Using Interval Timer Mode
When operating in interval timer mode, interval timer interrupts are generated at every overflow of
the counter. This enables interrupts to be generated at set periods.
1. Clear the WT/IT bit in WTCSR to 0, set the type of count clock in the CKS[2:0] bits in
WTCSR, and set the initial value of the counter in WTCNT.
2. Set the TME bit in WTCSR to 1 to start the count in interval timer mode.
3. When the counter overflows, the WDT sets the IOVF bit in WTCSR to 1 and an interval timer
interrupt request is sent to the INTC. The counter then resumes counting.
WTCNT value
H'FF
Overflow
Overflow
Overflow
Overflow
H'00
WT/IT = 0
ITI
ITI
ITI
TME = 1
[Legend]
ITI: Interval timer interrupt request generation
Figure 14.5 Operation in Interval Timer Mode
Time
ITI
Rev. 2.00 May. 08, 2008 Page 662 of 1200
REJ09B0344-0200