SH7211 Datasheet, PDF (580/1228 Pages) Renesas Technology Corp – 32-Bit RISC Microcomputer SuperHTM RISC engine Family

Section 10 Multi-Function Timer Pulse Unit 2 (MTU2)
10.7.9 Contention between TGR Read and Input Capture
If an input capture signal is generated in the T1 state of a TGR read cycle, the data that is read will
be the data in the buffer before input capture transfer for channels 0 to 4, and the data after input
capture transfer for channel 5.
Figures 10.124 and 125 show the timing in this case.
TGR read cycle
T1 T2
Pφ
Address
TGR address
Read signal
Input capture
signal
TGR
N
M
Internal data
bus
N
Figure 10.124 Contention between TGR Read and Input Capture (Channels 0 to 4)
TGR read cycle
T1 T2
Pφ
Address
TGR address
Read signal
Input capture
signal
TGR
N
M
Internal data
bus
M
Figure 10.125 Contention between TGR Read and Input Capture (Channel 5)
Rev. 2.00 May. 08, 2008 Page 556 of 1200
REJ09B0344-0200