SH7211 Datasheet, PDF (113/1228 Pages) Renesas Technology Corp – 32-Bit RISC Microcomputer SuperHTM RISC engine Family

Section 5 Exception Handling
5.4 Register Bank Errors
5.4.1 Register Bank Error Sources
(1) Bank Overflow
In the state where saving has already been performed to all register bank areas, bank overflow
occurs when acceptance of register bank overflow exception has been set by the interrupt
controller (the BOVE bit in IBNR of the INTC is set to 1) and an interrupt that uses a register
bank has occurred and been accepted by the CPU.
(2) Bank Underflow
Bank underflow occurs when an attempt is made to execute a RESBANK instruction while saving
has not been performed to register banks.
5.4.2 Register Bank Error Exception Handling
When a register bank error occurs, register bank error exception handling starts. The CPU operates
as follows:
1. The exception service routine start address which corresponds to the register bank error that
occurred is fetched from the exception handling vector table.
2. The status register (SR) is saved to the stack.
3. The program counter (PC) is saved to the stack. The PC value saved is the start address of the
instruction to be executed after the last executed instruction for a bank overflow, and the start
address of the executed RESBANK instruction for a bank underflow.
To prevent multiple interrupts from occurring at a bank overflow, the interrupt priority level
that caused the bank overflow is written to the interrupt mask level bits (I3 to I0) of the status
register (SR).
4. After jumping to the address fetched from the exception handling vector table, program
execution starts. The jump that occurs is not a delayed branch.
Rev. 2.00 May. 08, 2008 Page 89 of 1200
REJ09B0344-0200