SH7211 Datasheet, PDF (643/1228 Pages) Renesas Technology Corp – 32-Bit RISC Microcomputer SuperHTM RISC engine Family

Section 12 Port Output Enable 2 (POE2)
Bit Bit Name
14, 13 ⎯
Initial
Value
All 0
12
POE4F
0
11 to 9 —
All 0
8
PIE2
0
7, 6 POE7M[1:0] 00
R/W Description
R
Reserved
These bits are always read as 0. The write value should
always be 0.
R/(W)*¹ POE4 Flag
Indicates that a high impedance request has been input
to the POE4 pin.
[Clearing conditions]
• By writing 0 to POE4F after reading POE4F = 1
(when the falling edge is selected by bits 1 and 0 in
ICSR2)
• By writing 0 to POE4F after reading POE4F = 1 after
a high level input to POE4 is sampled at Pφ/8, Pφ/16,
or Pφ/128 clock (when low-level sampling is selected
by bits 1 and 0 in ICSR2)
[Setting condition]
• When the input condition set by bits 1 and 0 in ICSR2
occurs at the POE4 pin
R
Reserved
These bits are always read as 0. The write value should
always be 0.
R/W Port Interrupt Enable 2
Enables or disables interrupt requests when any one of
the POE4F and POE7F bits of the ICSR2 is set to 1.
0: Interrupt requests disabled
1: Interrupt requests enabled
R/W*²
POE7 Mode
These bits select the input mode of the POE7 pin.
00: Accept request on falling edge of POE7 input
01: Accept request when POE7 input has been sampled
for 16 Pφ/8 clock pulses and all are at a low level.
10: Accept request when POE7 input has been sampled
for 16 Pφ/16 clock pulses and all are at a low level.
11: Accept request when POE7 input has been sampled
for 16 Pφ/128 clock pulses and all are at a low level.
Rev. 2.00 May. 08, 2008 Page 619 of 1200
REJ09B0344-0200