SH7211 Datasheet, PDF (140/1228 Pages) Renesas Technology Corp – 32-Bit RISC Microcomputer SuperHTM RISC engine Family

Section 6 Interrupt Controller (INTC)
6.4.5 On-Chip Peripheral Module Interrupts
On-chip peripheral module interrupts are generated by the following on-chip peripheral modules:
• A/D converter (ADC)
• Direct memory access controller (DMAC)
• Compare match timer (CMT)
• Bus state controller (BSC)
• Watchdog timer (WDT)
• Multi-function timer pulse unit 2 (MTU2)
• Multi-function timer pulse unit 2S (MTU2S)
• Port output enable 2 (POE2)
• I²C bus interface 3 (IIC3)
• Serial communication interface with FIFO (SCIF)
• WAVE interface (WAVEIF)
As every source is assigned a different interrupt vector, the source does not need to be identified in
the exception service routine. A priority level in a range from 0 to 15 can be set for each module
by interrupt priority registers 05 to 15 (IPR05 to IPR15). The on-chip peripheral module interrupt
exception handling sets the I3 to I0 bits in SR to the priority level of the accepted on-chip
peripheral module interrupt.
Rev. 2.00 May. 08, 2008 Page 116 of 1200
REJ09B0344-0200