SH7211 Datasheet, PDF (632/1228 Pages) Renesas Technology Corp – 32-Bit RISC Microcomputer SuperHTM RISC engine Family

Section 12 Port Output Enable 2 (POE2)
12.1 Features
• Each of the POE0, POE1, POE3, POE4, POE7, and POE8 input pins can be set for falling
edge, Pφ/8 × 16, Pφ/16 × 16, or Pφ/128 × 16 low-level sampling.
• High-current pins and the pins for channel 0 of the MTU2 can be placed in high-impedance
state by POE0, POE1, POE3, POE4, POE7, and POE8 pin falling-edge or low-level sampling.
• High-current pins can be placed in high-impedance state when the high-current pin output
levels are compared and simultaneous active-level output continues for one cycle or more.
• High-current pins and the pins for channel 0 of the MTU2 can be placed in high-impedance
state by modifying the POE2 register settings.
• Interrupts can be generated by input-level sampling or output-level comparison results.
The POE2 has input level detection circuits, output level comparison circuits, and a high-
impedance request/interrupt request generating circuit as shown in the block diagram of figure
12.1.
Rev. 2.00 May. 08, 2008 Page 608 of 1200
REJ09B0344-0200