SH7211 Datasheet, PDF (1223/1228 Pages) Renesas Technology Corp – 32-Bit RISC Microcomputer SuperHTM RISC engine Family

Single write............................................. 257
Single-cycle scan mode .......................... 781
Slave receive operation........................... 752
Slave transmit operation ......................... 749
Sleep mode ........................................... 1005
Slot illegal instructions ............................. 94
Software protection................................. 941
Software standby mode......................... 1005
SRAM interface with byte selection ....... 280
Stack after interrupt exception
handling .................................................. 128
Stack status after exception handling
ends........................................................... 97
Standby control circuit.............................. 64
Status register (SR) ................................... 16
Supported DMA transfers....................... 336
System control instructions....................... 50
T
T bit .......................................................... 23
TAP controller ...................................... 1015
TDO output timing ............................... 1016
The address map for the operating
modes........................................................ 58
Timing to clear an interrupt source......... 141
Transfer rate............................................ 731
Trap instructions ....................................... 94
Types of exception handling and
priority order ............................................. 77
U
Unconditional branch instructions
with no delay slot ...................................... 23
User boot mode ....................................... 935
User break controller (UBC)................... 143
User break interrupt ................................ 114
User debugging interface (H-UDI) ....... 1011
User MAT ............................................... 892
User program mode................................. 924
Using interval timer mode....................... 662
Using watchdog timer mode ................... 660
V
Vector base register (VBR)....................... 17
W
Wait between access cycles .................... 286
Watchdog timer (WDT) .......................... 649
WAVE Interface (WAVEIF) ................ 1019
Rev. 2.00 May. 08, 2008 Page 1199 of 1200
REJ09B0344-0200