SH7211 Datasheet, PDF (1155/1228 Pages) Renesas Technology Corp – 32-Bit RISC Microcomputer SuperHTM RISC engine Family

Section 27 Electrical Characteristics
27.4.10 IIC3 Module Timing
Table 27.15 I²C Bus Interface 3 Timing
Conditions: Vcc = PLLVcc = 1.4 V to 1.6 V, VccQ = 3.0 V to 3.6 V,
Vss = PLLVss = VssQ = 0 V, Ta = −40°C to +85°C
Specifications
Item
Symbol Test Conditions Min.
Typ. Max.
SCL input cycle time
t
SCL
SCL input high pulse width
t
SCLH
SCL input low pulse width
t
SCLL
SCL, SDA input rise time
t
Sr
SCL, SDA input fall time
t
Sf
SCL, SDA input spike pulse
t
SP
removal time*²
12 t + 600
—
pcyc
3 t + 300
—
pcyc
5 t + 300
—
pcyc
—
—
—
—
—
—
—
—
—
300
1t
pcyc
1t
pcyc
SDA input bus free time
t
BUF
Start condition input hold time t
STAH
Retransmit start condition input
t
STAS
setup time
5
—
—
3
—
—
3
—
—
Stop condition input setup time t
3
STOS
Data input setup time
t
SDAS
1 t + 20
pcyc
Data input hold time
t
0
SDAH
SCL, SDA capacitive load
Cb
0
SCL, SDA output fall time*³
t
Sf
PV = 3.0 to 3.6 V —
CC
Notes: 1. t_pcyc indicates peripheral clock (Pφ) cycle.
2. Depends on the value of NF2CYC.
3. Indicates the I/O buffer characteristic.
—
—
—
—
—
—
—
400
—
300
Unit Figure
ns Figure 27.48
ns
ns
t *¹
pcyc
ns
ns
t *1
pcyc
t *1
pcyc
t *1
pcyc
t *1
pcyc
ns
ns
pF
ns
Rev. 2.00 May. 08, 2008 Page 1131 of 1200
REJ09B0344-0200