SH7211 Datasheet, PDF (196/1228 Pages) Renesas Technology Corp – 32-Bit RISC Microcomputer SuperHTM RISC engine Family

Section 7 User Break Controller (UBC)
(3) Break Condition Specified for I Bus Data Access Cycle
(Example 3-1)
• Register specifications
BBR_0 = H'0094, BAR_0 = H'00314156, BAMR_0 = H'00000000,
BBR_1 = H'12A9, BAR_1 = H'00055555, BAMR_1 = H'00000000, BRCR = H'00000000
<Channel 0>
Address: H'00314156, Address mask: H'00000000
Bus cycle: I bus/instruction fetch/read (operand size is not included in the condition)
<Channel 1>
Address: H'00055555, Address mask: H'00000000
Bus cycle: I bus/data access/write/byte
On channel 0, the setting of I bus/instruction fetch is ignored.
On channel 1, a user break occurs when the DMAC writes byte data in address H'00055555 on
the I bus (write by the CPU does not generate a user break).
Rev. 2.00 May. 08, 2008 Page 172 of 1200
REJ09B0344-0200